1. Field of the Invention
The present disclosure generally relates to the field of integrated circuits, and, more particularly, to a back end of line processing for providing highly conductive contact pads based on copper and the like in sophisticated metallization structures.
2. Description of the Related Art
The manufacturing of integrated circuits involves many complex process steps to form circuit elements, such as transistors, capacitors, resistors and the like, in and above an appropriate semiconductor material. In recent years, enormous advances have been made in increasing integration density and overall functionality of the integrated circuits. These advances have been achieved by scaling the individual circuit elements to dimensions in the deep sub-micrometer range, with currently used critical dimensions, such as the gate length of a field effect transistor, of 30 nm and less. Hence, millions of circuit elements may be provided in a die region, wherein a complex interconnect fabric may have to be designed, in which typically each circuit element may be electrically connected to one or more other circuit elements. These interconnect structures are typically established in a metallization system comprising one or more wiring levels, in which appropriate metal features are formed according to the circuit configuration under consideration in a similar manner as a multi-level printed circuit board, wherein, however, the dimensions of the metal features have to be adapted to the dimensions of the semiconductor circuit elements, such as the transistors, and the like.
Over many decades, aluminum has been used as the metal of choice for forming the metal features in the metallization layers of the semiconductor devices due to its moderately high thermal and electrical conductivity, its self-limiting creation of a passivating oxide layer and its compatibility with other materials and process techniques used for fabricating integrated devices. With the continuous reduction of the circuit dimensions, the dimensions of the metal features have resulted in a situation in which the overall signal delay in the devices is no longer restricted by the performance of the individual semiconductor circuit elements, such as the switching speed of the transistors, but is substantially determined by the parasitic time constants in the metallization system caused by the restricted conductivity of aluminum and the parasitic capacitance between neighboring metal regions. Therefore, in modern integrated circuits, highly conductive metals, such as copper and alloys thereof, are used to accommodate the high current densities encountered during the operation of the devices, while the parasitic capacitance may be reduced by using low-k dielectric materials, which are to be understood as dielectrics having a dielectric constant of 3.0 or less.
In an advanced stage of the manufacturing of integrated circuits, it is usually necessary to package a chip and provide leads and terminals for connecting the chip circuitry with the periphery. In some packaging techniques, chips, chip packages or other appropriate units may be connected by means of solder balls, formed from so-called solder bumps, that are formed on a corresponding layer of at least one of the units, for instance on a dielectric passivation layer of the microelectronic chip. In order to connect the microelectronic chip with the corresponding carrier, the surfaces of two respective units to be connected, i.e., the microelectronic chip comprising, for instance, a plurality of circuits, and a corresponding package, have formed thereon adequate pad arrangements to electrically connect the two units after reflowing the solder bumps provided at least on one of the units, for instance, on the microelectronic chip. In other techniques, solder bumps may have to be formed that are to be connected to corresponding wires, or the solder bumps may be brought into contact with corresponding pad areas of another substrate acting as a heat sink. Consequently, it may be necessary to form a large number of solder bumps that may be distributed over the entire chip area, thereby providing, for example, the I/O (input/output) capability, as well as the desired low-capacitance arrangement required for high frequency applications of modern microelectronic chips that usually include complex circuitry, such as microprocessors, storage circuits and the like, and/or include a plurality of integrated circuits forming a complete complex circuit system.
Another approach for connecting chips with a package includes wire bonding techniques, which have been successfully developed over many decades on the basis of aluminum and are still well established and represent the dominant technology for connecting the fast majority of semiconductor chips to a carrier substrate, wherein usually aluminum-based bond pads are provided, which are contacted by an appropriate wire made of aluminum, copper, gold and the like. During the wire bonding process, the bond wire is then at one end brought into contact with the bond pad. Upon applying pressure, elevated temperature and ultrasonic energy, the wire, which may have formed thereon a ball, if required, is welded to the bond pad so as to form an intermetallic connection. Thereafter, the other end of the bond wire may be bonded to a lead pin of the package, in which the semiconductor chip is mechanically fixed during the bond process.
However, many advanced semiconductor devices may have a copper-based metallization structure in view of device performance, integration density and process compatibility in facilities fabricating a wide variety of different products, wherein, however, the connection to the carrier substrate or the package is to be established by wire bonding due to less demanding I/O capabilities as compared to, for instance, CPUs and other highly complex ICs, and the economic advantages of the wire bonding techniques over complex bump-based techniques. For example, sophisticated memory devices may require very complex high performance metallization systems, while the I/O capacity may be readily achieved on the basis of wire bonding. In a production environment, however, the wire bonding on copper bond pads is very difficult to achieve due to an inhomogeneous self-oxidization of the copper surface in combination with extensive corrosion, which may result in highly non-reliable bond connections. That is, the bond pads and the bond wires connected thereto may suffer from pronounced corrosion, in particular when exposed to sophisticated environmental conditions, as may occur during normal operation and in particular during test periods performed at elevated temperatures.
Many types of advanced semiconductor devices, however, may have a copper-based metallization structure in view of device performance, integration density and process compatibility in semiconductor facilities that fabricate a wide variety of different products, wherein, however, the connection to the carrier substrate or the package is to be established by wire bonding due to less demanding I/O capabilities as compared to, for instance, CPUs and other highly complex integrated circuits, and due to the economic advantages of the wire bonding techniques over complex bump based techniques. For example, sophisticated memory devices may require very complex high performance metallization systems while the I/O capacity may be readily achieved on the basis of wire bonding. In a production environment, the wire bonding on copper bond pads may require non-corroded surface areas in order to allow a reliable inter-metallic connection between the bond wire and the copper-containing contact surface.
Irrespective of whether complex bump structures of wire bonding techniques are to be applied for connecting the semiconductor chip with an appropriate carrier material or package, typically different manufacturing environments are involved in forming the complex metallization system on the one hand and performing final manufacturing steps including the dicing and packaging of the semiconductor chips on the other hand. A corresponding splitting of the manufacturing process, as is well established in current semiconductor fabrication infrastructures, may involve additional problems with respect to complex copper-based metallization systems, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a very advanced manufacturing stage. The device 100 comprises a substrate 101, such as a silicon material, or any other appropriate carrier material for forming thereon a semiconductor layer 102, in and above which circuit elements 103 are formed. For example, the circuit elements 103 may include transistors, capacitors, resistors and the like, as required for implementing the desired circuit function. Furthermore, a metallization system 150 is formed above the circuit elements 103 and typically comprises a plurality of metallization layers 151, 152, 153, 154, each of which comprises at least corresponding metal lines so as to provide inner-level electrical connections, while vertical contacts or vias are provided so as to electrically connect one metallization layer with a neighboring metallization layer. For example, the metallization layer 151 comprises an appropriate dielectric material 151A which may include sophisticated low-k dielectric materials in which are embedded metal lines or regions 151B, which are typically formed on the basis of copper material, as discussed above. Similarly, the metallization layer 152 may comprise a dielectric material 152A in combination with metal features 152B, wherein a cap layer 152C may be provided so as to reliably cover any metal features of the metallization layer 151 and also to act as an etch stop material upon patterning the dielectric material 152A. For example, typical materials used for a cap layer are silicon nitride, nitrogen-enriched silicon carbide and the like. Similarly, the metallization layer 153 may comprise a dielectric material 153A and corresponding metal features 153B followed by a cap layer 154C. The metallization layer 154 represents the final or very last metallization layer of the system 150 and comprises an appropriate dielectric material 154A in combination with metal regions 154B, which are also considered as contact regions in order to receive appropriate bump elements or to receive a bond wire in a later manufacturing stage. As discussed above, the metal regions 154B may comprise a copper material and may thus have a copper-containing surface 154S, which is also referred to as a contact surface. Moreover, a cap layer 155C is formed on the metallization layer 154 in order to appropriately confine the metal features 154B and enable appropriate patterning processes to be performed on a passivation layer stack 160, which may comprise a plurality of different material layers, such as layers 161, 162 and the like. Typically, the passivation layer stack 160 may comprise materials such as silicon dioxide, silicon oxynitride, silicon nitride and the like.
The semiconductor device 100 as shown in FIG. 1a is formed on the basis of any appropriate process strategy, wherein the substrate 101 is processed on wafer bases, that is, a plurality of semiconductor die regions are provided in or on the substrate 101 in order to form a plurality of substantially identical semiconductor devices. To this end, typically a semiconductor facility comprises a plurality of process modules, such as lithography modules, etch modules, anneal modules, implantation modules and the like, in which the substrates 101 are processed in accordance with dedicated process recipes in compliance with the requirements of the semiconductor device 100. Hence, after completing the semiconductor-based circuit elements 103, the metallization system 150 is formed by using sophisticated process techniques which may typically include the deposition of an appropriate dielectric material and patterning the same so as to form respective openings therein, which are subsequently filled with a copper-based material in combination with appropriate barrier materials (not shown), followed by the removal of any excess material. Hence, layer after layer, the plurality of metallization layers 151, 152, 153, 154 are formed by applying basically the same process strategy, wherein, however, the corresponding critical dimensions may have to be adapted to the metallization layer under consideration. Finally, the very last metallization layer 154 is formed so as to include the contact regions 154B so as to be appropriately positioned and having an appropriate lateral size in compliance with the further processing, i.e., with forming solder bumps or providing bond areas for a wire bond process. After forming the cap layer 155C, the layer stack 160 is deposited on the basis of well-established process techniques, wherein typically a further patterning process may be applied on the basis of lithography techniques and plasma-based etch recipes.
FIG. 1b schematically illustrates the device 100 in a further advanced manufacturing stage. As shown, openings 160A are formed in the passivation layer stack 160 and may also extend through the cap layer 155C, thereby exposing a portion of the surface 154S. To this end, any appropriate plasma-based etch recipes may be applied in combination with lithography techniques. As shown, the processing up to this manufacturing stage may be performed on the basis of the substrate 101 comprising a plurality of die regions 110. Frequently, the further processing may be continued in a remote manufacturing facility in which dedicated process equipment and manufacturing strategies are implemented so as to finalize the device 100, which typically includes the formation of an appropriate bump structure or performing wire bonding processes after dicing the substrate into individual semiconductor chips. Consequently, as indicated by 140, the substrate 101 may be transported to a different manufacturing environment which, however, may result in a certain degree of surface contamination, for instance by oxidation and the like, by forming a highly irregular surface which may result in corresponding yield losses upon forming an appropriate bump structure or performing a wire bond process on the basis of the surface 154S contaminated during the transport 140.
Consequently, it has been suggested to transport the devices 100 prior to actually patterning the passivation layer stack 160, which, however, may require significant additional resources in the remote manufacturing facility since lithography processes in combination with plasma-based etch processes have to be carried out. In other approaches, the contact regions 154B may receive a terminal metal layer (not shown), for instance comprised of aluminum, which has been a well-established material for forming thereon bump structures or performing a wire bond process. In this case, however, significant additional resources have to be provided in the manufacturing environment in which the metallization system 150 is fabricated.
FIG. 1d schematically illustrates a cross-sectional view of the device 100 in a further advanced manufacturing stage in which a further passivation layer 170, such as a polyamide layer, may be provided, wherein solder bumps 171 may be formed so as to connect to the contact surface 154S. To this end, the material 170 may be applied and may be subsequently patterned by well-established process techniques for polyamide material, followed by the deposition of conductive materials, such as materials 171B, in order to provide appropriate interface characteristics with respect to a further material 171a, such as a lead-free solder material and the like. Consequently, if the processing of the device 100 for forming the polyamide material 170 and the bump structure 171 is performed in the remote manufacturing site, the deteriorated surface 154S (FIG. 1c) may result in significant yield loss unless significant reworking is performed, which, however, may require additional process tool resources which are typically not available in any such manufacturing sites. On the other hand, providing a dedicated terminal metal layer, such as aluminum, or forming the bump structure 171 in the same manufacturing facility in which the metallization system 150 is formed, may require additional resources, which is frequently not compatible with the existing equipment and configuration of semiconductor manufacturing facilities.
In view of the situation described above, the present disclosure relates to manufacturing strategies and semiconductor devices in which complex copper-based metallization systems may be formed up to a manufacturing stage in which the finalizing, i.e., the polyamide processing and the contact processing, may be performed in a remote manufacturing environment, while avoiding, or at least reducing, the effects of one or more of the problems identified above.